Title: Dynamic Performance Tuning for Speculative Threads
Speaker: Prof. Antonia Zhai, University of Minnesota
Time: 2:20pm, May 27 (Wed), 2009
Place: Room 111, CSIE building

Abstract:

With the emergence of multicore processors, being able to efficiently extract parallelism from sequential applications efficiently is become increasingly important. Thread-Level Speculation (TLS) aims to ease automatic parallelization by allowing potentially dependent threads to execute speculatively in parallel. While TLS offers performance potential for applications that are otherwise non-parallel, extracting speculative threads in the presence of complex control flow and ambiguous data dependences is a real challenge.   This task is further complicated by the fact that the performance of speculative threads are often architectural dependent, input-sensitive, and even exhibit phase behavior.

In this talk, I will discuss hardware and software support that takes advantage of runtime performance profile to extract efficient speculative threads. In the proposed framework, speculative threads are monitored by hardware-based performance counters; and their performance impact is determined.  The creation of speculative threads is adjusted based on this estimation.  This paper proposed a speculative threads performance estimation algorithm, which is capable of correctly determine whether speculation is able to improve performance for loops that correspond to over 80% of total loop execution time on average.  With our best dynamic performance tuning policy, we are able to achieve an overall speedup of 53% on a set of benchmarks from SPEC2000 suite, and outperform profile-based static thread selection by 12%.

Short Biography:

Antonia Zhai is an assistant professor in the Department of Computer Science and Engineering at the University of Minnesota.  She received her Ph.D. degree in Computer Science from Carnegie Mellon University in 2005 for her research on developing advanced compiler technologies to exploit the potential of thread-level speculation for general-purpose applications. Prior to that, she received her B.A.Sc. and M.A.Sc. degrees in Computer Engineering from the University of Toronto in 1996 and 1998 respectively. She is interested in developing novel compiler optimizations and architecture features not only to improve the performance for such processors, but also to enhance non-performance features, such as programmability, security, testability and reliability.